A multi-step process is involved in the generation of a layout of an IC. An initial design typically undergoes revisions due to design for manufacturing (DFM) guidelines. That is, the initial design is revised to conform to the automated manufacturing process. These guidelines often impose the need for corrections inserted into areas within the design data flow. At times, this may require drastic modifications to the data, both during the layer derivation or design rule check (DRC) phase. This is especially true during the resolution enhancement technology (RET) phase, such as optical proximity correction (OPC).
One example of this problem may be described with reference to U.S. Pat. No. 6,792,592. More specifically, advances in IC technology have largely been accomplished by decreasing the feature size of circuit elements on the semiconductor chip. As the feature size continues to decrease, problems arise as a consequence of the optical lithography process used to manufacture the ICs that affect the circuit design. Namely, the process generally begins with the formation of a photoresist layer on the surface of a semiconductor wafer. A mask (which is also meant to include the term “reticle” herein) composed of opaque regions and light-transmissive clear regions is then positioned over the photo resist layer. Light is shone on the mask from a light source or some other type of electromagnetic radiation.
The light is reduced and focused through an optical system that contains a number of lenses, filters and minors to pass through the clear regions of the mask and expose the underlying photoresist layer while other portions of the photoresist layer underlying the opaque regions of the mask are unexposed. The exposed photoresist layer is then developed, through chemical removal of either the exposed or non-exposed regions of the photoresist layer. The end result is a semiconductor wafer with a photoresist layer having a desired pattern. This pattern can then be used for etching underlying regions of the wafer.